Delta 1.07 VFD-D D User Manual download pdf (Page 95)

Chapter 4 Parameter Settings|DD Series

4-71

‘A’

‘0’

‘9’

LRC Check

‘A’

END

RTU mode:

Command message: Response message:

ADR 01H ADR 01H

CMD1 10H CMD 1 10H

05H 05H

Starting data address

00H

Starting data address

00H

00H 00H

Number of data

(count by word)

02H

Number of data

(count by word)

02H

Number of data

(count by byte)

CRC Check Low

41H

13H CRC Check High 04H

The first data content

88H

0FH

The second data content

A0H

CRC Check Low ‘9’

CRC Check High ‘A’

Check sum

ASCII mode:

LRC (Longitudinal Redundancy Check) is calculated by summing up, module 256 and the values of the

bytes from ADR1 to last data character then calculating the hexadecimal representation of the

2’s-complement negation of the sum.

For example,

01H+03H+21H+02H+00H+02H=29H, the 2’s-complement negation of 29H is D7H.

RTU mode:

CRC (Cyclical Redundancy Check) is calculated by the following steps:

Step 1: Load a 16-bit register (called CRC register) with FFFFH.

Step 2: Exclusive OR the first 8-bit byte of the command message with the low order byte of the 16-bit

CRC register, putting the result in the CRC register.

Step 3: Examine the LSB of CRC register.

Step 4: If the LSB of CRC register is 0, shift the CRC register one bit to the right with MSB zero filling,

then repeat step 3. If the LSB of CRC register is 1, shift the CRC register one bit to the right with MSB

zero filling, Exclusive OR the CRC register with the polynomial value A001H, then repeat step 3.

Step 5: Repeat step 3 and 4 until eight shifts have been performed. When this is done, a complete 8-bit

byte will have been processed.

1 2 ... 90 91 92 93 94 95 96 97 98 99 100 ... 140 141

Comments to this Manuals

No comments

Delta 1.07 VFD-D D User Manual Page 95

Comments to this Manuals