Delta 35 Specifications Page 1

Rev. 0.2 2/05 Copyright © 2005 by Silicon Laboratories AN217AN217C8051F35X DELTA-SIGMA ADC USER’S GUIDE1. IntroductionDelta-sigma analog-to-digital

AN21710 Rev. 0.2SFR Definition 2.5. ADC0MD: ADC0 ModeBit 7: AD0EN: ADC0 Enable Bit.0: ADC0 Disabled. ADC is in low-power shutdown.1: ADC0 Enabled. A

AN217Rev. 0.2 113. Hardware DesignDesigning a low-noise, high-precision measurement system requires not only proper ADC configuration, butcareful cir

AN21712 Rev. 0.2Figure 5. Single-Ended Measurements and Ground Circuits: Poor PerformanceFigure 6. Differential Measurements Reject Common-Mode NoiseF

AN217Rev. 0.2 134. Delta-Sigma Noise SpecificationsDelta-sigma converters make high-precision, high-resolution measurements of signals. Often, the me

AN21714 Rev. 0.24.1. Effective ResolutionMany ADC applications measure a dynamic signal in the presence of noise. Noise sources include the ADC itsel

AN217Rev. 0.2 15Table 1 is a copy of the posted specification of the ADC0’s typical noise table from the C8051F35x family datasheet. This table shows

AN21716 Rev. 0.2DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.2 Updated text on page 15.

AN217Rev. 0.2 17NOTES:

AN21718 Rev. 0.2CONTACT INFORMATIONSilicon Laboratories Inc.4635 Boston LaneAustin, TX 78735Tel: 1+(512) 416-8500Fax: 1+(512) 416-9669Toll Free: 1+(87

AN2172 Rev. 0.22. Using the C8051F35x Delta-Sigma ADCUsing delta-sigma ADCs require an understanding of how to properly configure the modulator, use

AN217Rev. 0.2 3 Resistor: The resistor value should be high enough for isolation (i.e., at least 10s of ohms) but not too high to cause settling time

AN2174 Rev. 0.22.2.1. Voltage ReferenceThe voltage reference circuit should be treated as carefully as the measured signal, because noise on the volta

AN217Rev. 0.2 52.2.3. Offset DACThe ADC features an internal dedicated DAC that is used to adjust the measurement offset of the ADC. This canbe used a

AN2176 Rev. 0.2Once the modulator clock is configured, the modulator sample rate of the ADC is also set to MDCLK/128.Therefore, the typical sample rat

AN217Rev. 0.2 72.2.6. The Digital FilterFigure 4. Digital Filter Frequency Response (SINC3)The filter’s function is to convert the 1-bit digital outpu

AN2178 Rev. 0.2SFR Definition 2.3. ADC0DECH: ADC0 Decimation Ratio Register High ByteSFR Definition 2.4. ADC0DECL: ADC0 Decimation Ratio Register Low

AN217Rev. 0.2 9The ADC’s digital filter gives two options for output: FAST and SINC3. The FAST filter uses results from only thecurrent conversion cyc