Delta 35 Specifications download pdf (Page 6)

AN217

6 Rev. 0.2

Once the modulator clock is configured, the modulator sample rate of the ADC is also set to MDCLK/128.

Therefore, the typical sample rate is 2.4576 MHz/128 = 19.2 kHz. This will be well above the signal bandwidth

measured, as the maximum output word rate for the ADC is 1 kHz.

SFR Definition 2.2. ADC0CLK: ADC0 Modulator Clock Divisor

Bits 7–0: ADC0CLK: ADC0 Modulator Clock Divisor.

This register establishes the Modulator Clock (MDCLK), by dividing down the system clock

(SYSCLK). The input signal is sampled by the modulator at a frequency of MDCLK / 128. For opti-

mal performance, the divider should be chosen such that the modulator clock is equal to

2.4576 MHz (modulator sampling rate = 19.2 kHz).

The system clock is divided according to the equation:

MDCLK = SYSCLK / (ADC0CLK + 1)

Note: The Modulator Sampling Rate is not the ADC Output Word Rate.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

ADC0CLK 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFR Address:

0xF7

1 2 3 4 5 6 7 8 9 10 11 ... 17 18

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Delta 35 Specifications Page 6