Delta 45 Specifications

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ADC12EU050
www.ti.com
SNAS444I JANUARY 2008REVISED APRIL 2013
ADC12EU050 Ultra-Low Power, Octal, 12-bit, 45 MSPS Sigma-Delta Analog-to-Digital
Converter
Check for Samples: ADC12EU050
1
FEATURES
DESCRIPTION
The ADC12EU050 is a 12-bit, ultra-low power, octal
2
Xignal
CT∑Δ ADC Technology
A/D converter for use in high performance analog to
45MSPS Sampling Rate
digital applications. The ADC12EU050 uses an
Anti-Alias Filter Free Nyquist Sample Range
innovative continuous time sigma delta architecture
offering ultra low power consumption and an alias
Unique Instant Overload Recovery (IOR)
free sample bandwidth up to 22.5MHz. The input
Wide 2.10 V
PP
Input Range
stage of each channel features a proprietary system
1.2V Supply Voltage
to ensure instantaneous recovery from overdrive.
Instant overload recovery (IOR) with no memory
Integrated Precision LC PLL
effect ensures the elimination of phase errors
Serial Control via SPI Compatible Interface
resulting from out of range input signals. The
ADC12EU050 reduces interconnection complexity by
APPLICATIONS
using programmable serialized outputs which offer
the industry standard LVDS and SLVS modes. Power
Medical Imaging, Ultrasound
consumption of only 46mW per channel @ 45MSPS
Industrial Ultrasound, such as Non-Destructive
gives a total chip power consumption of 364mW. The
Testing
ADC12EU050 can operate entirely from a 1.2V
Communications
supply, although a separate output driver supply of up
to 1.8V can be used. The device operates from 0 to
Battery Powered Portable Systems
+70 °C and is supplied in a 10 x 10 mm
2
, 68-pin
VQFN package.
KEY SPECIFICATIONS
Resolution 12 Bits
Conversion Rate 45 MSPS
SNR : 69.3 dBFS (typ) @ 45 MSPS
f
IN
= 4.4MHz
THD –76.6 dB (typ) @ 45 MSPS
f
IN
= 4.4MHz
Per Channel Power 46 mW/ch (typ) @ 45 MSPS
Total Active Power 364 mW (typ) @ 45 MSPS
Inter-Channel Isolation >110 dB @
f
IN
= 4.4 MHz
Operating Temp. Range 0 to +70 °C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Summary of Contents

Page 1 - Converter

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013ADC12EU050 Ultra-Low Power, Octal, 12-bit, 45 MSPS Sigma-Delta Analog-to-DigitalConverter

Page 2

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comAC AND TIMING CHARACTERISTICSUnless otherwise specified, the following conditions apply:

Page 3

D1 D2 D3 D4 D5D6D7 D9D8 D11 D0 D1 D2 D3D11D10 D4 D5BCLK+WCLK-Output dataSystem ClocktHtStBCLKtDVtRSample nSample n+1WCLK+BCLK-DOn+DOn-Word ClockBit Cl

Page 4

tRStRHA7 D7 D0tSSELHI,,SCLKSDATASSELA7D7 D0SCLKSDATASSEL90%10%90%10%tSCLKRtSCLKFtSSELStSCLKtSCLKLtWStWHtSSELHtSCLKHR/WVDRVOCM0Differential output sign

Page 5

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013FUNCTIONAL DESCRIPTIONThe ADC12EU050 employs a number of unique strategies to provide a h

Page 6

OPAMPVIN+VIN-CLKOPAMPVIN+VIN-CLKCLKCLKCLKCLKADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comFigure 6. SHA Input StageFigure 7. Continuous

Page 7

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Figure 8. Instant Overload RecoveryINTEGRATED PRECISION LC PLLThe ADC12EU050 family inclu

Page 8

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comSuch steep digital filters introduce group delay problems, but the ADC12EU050 includes a

Page 9

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013UNCORRELATED NOISE REFERENCE FOR EACH CHANNELIn many early multi-channel ADC designs, a s

Page 10 - ADC12EU050

-80-60-40-200GAIN (dB)101102103104105OFFSET (Hz)2040106107108Loop Bandwidth at 0.415 MHzLoop Bandwidth at 1.50 MHz-80-60-40-200GAIN (dB)10110210310410

Page 11

1st stage of ÐÂ ModulatorVIN+VIN-ADC1st stage of ÐÂ ModulatorVIN+VIN-ADCVCMRecommended transformer:Mini-circuits T1-6TADC12EU050www.ti.comSNAS444I –JA

Page 12

SLEEPRSTReference and BiasRefselectIRef0.5VCLK+ (SE)CLK-VINn+VREFTVREFBRREFSDATASCLKDCRegisterADC12EU050DOn+DOn-RegisterTo RegistersCMOS INSPI Control

Page 13

1st stage of ÐÂ ModulatorVIN+VIN-ADCDifferential Input pDifferential Input nREXTREXTADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comThe A

Page 14

LVDSClassic full bridgeBias PBias NVDR = 1.8VVIN+VIN-VOCM = 1.25VVOUT+Optional internal 1005 terminationVOUT-Reduced Common Mode LVDSHalf BridgeVDD Re

Page 15

SLVSHalf BridgeVSS ReferencedBias PVDR = 1.2VVIN+VIN-VOCM = 175 mVVOUT+Optional internal 1005 terminationVOUT-ADC12EU050SNAS444I –JANUARY 2008–REVISED

Page 16

CH0 SerializerCH7 SerializerTSEL[0]TSEL[1]From Decimator Control Register 16hTraining Sequence 3:Custom PatternTraining Sequence 2:101010101010Trainin

Page 17

ADC1RREFVREFTVREFBADC2RREFVREFTVREFBADCnRREFVREFTVREFBAGNDplane10 k5(± 1%)10 k5(± 1%)10 k5(± 1%)Digital Filter saturates at IOR mode full scale, deter

Page 18

DCAPDACBiasDACRDCAPCDCAP1.5 k5ADC12EU050 ä? ModulatorAGNDADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013DCAPCAPACITOR SELECTIONThe DCAPp

Page 19

100 nF505100 nF100 nF100 nF47 µFVIN0+VIN0-VIN1+VIN1-CLK+ (SE)CLK-VREFTVREFBDCAPRSTSLEEPSSELSCLKSDATADO0+DO0-DO1+DO1-DO2+DO2-DO3+DO3-DO4+DO4-DO5+DO5-DO

Page 20

ADCSPIController(Master)e.g. DSP,Microcontroller,FPGAserial_inclockchip_select_b_1serial_outoutput_enableVDADCSDATASCLKSSELchip_select_b_NSDIO Pads co

Page 21

If R/W = 1 (read), the SPI drives SDATA.If R/W = 0 (write), SDATA is driven from externally.SDATA is driven from externallySDATASSELSCLKA7 A6 A5 A4 A3

Page 22

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Register IndexAddress b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] DefaultTop Control Register

Page 23

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 521234567891011121314151617515049484746454443424140393837363518 19 20 21 22 23 24 25 26 27 28 29 30 31

Page 24

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comBit DescriptionThe SRES is self clearing in approximately 2µs.0 Software Reset Inactive1

Page 25

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Bit Description1 PD1: Power Down Channel 10 Channel Active1 Channel Power Down0 PD0: Powe

Page 26

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comPLL Control Register• Address: 08h• Attributes: Write Only• Register 09h reads back conte

Page 27

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Bit Description2 20HYS: Enable 20mV hysteresis. This bit enables 20mV hysteresis. It shou

Page 28

DGF = 32 + 4 x DGFa + DGFb26ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comDecimator Clipping Control Register• Address: 14h• Attributes

Page 29

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Coefficent a[2:0] Coefficent b[2:0] Digital Gain (dB) Equivalent full scaleinput range (V

Page 30

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comBit Description1:0 TSEL[1:0]: Training Sequence Select. These bits select the LVDS output

Page 31

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Chip ID Register• Address: 1Eh• Attributes: Read Onlyb[7] b[6] b[5] b[4] b[3] b[2] b[1] b

Page 32

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comREVISION HISTORYChanges from Revision H (April 2013) to Revision I Page• Changed layout o

Page 33

PACKAGE OPTION ADDENDUMwww.ti.com13-Sep-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEc

Page 34 - 32 + 4 x DGFa + DGFb

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comPIN DESCRIPTIONSPin No. Name Type Function and ConnectionANALOG I/O2 VIN0+3 VIN0-67 VIN1+

Page 35

PACKAGE OPTION ADDENDUMwww.ti.com13-Sep-2014Addendum-Page 2

Page 36

www.ti.comPACKAGE OUTLINECPIN 1 ID0.9 MAX0.050.004X868X 0.30.264X 0.568X 0.70.54X (45 X0.42)7.7 0.1B10.19.9A10.19.9(0.2)VQFN - 0.9 mm max heightNKE00

Page 37

www.ti.comEXAMPLE BOARD LAYOUT68X (0.8)68X (0.25)( 7.7)(9.6)64X (0.5)( ) TYPVIA0.20.07 MAXALL AROUND0.07 MINALL AROUND(9.6)(1.19) TYP(1.19)TYPVQFN - 0

Page 38

www.ti.comEXAMPLE STENCIL DESIGN(9.6)68X (0.8)68X (0.25)64X (0.5)(1.19) TYP(1.19)TYP(9.6)36X(0.99)VQFN - 0.9 mm max heightNKE0068APLASTIC QUAD FLATPAC

Page 39 - PACKAGE OPTION ADDENDUM

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

Page 40

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013PIN DESCRIPTIONS (continued)Pin No. Name Type Function and ConnectionWord Clock. Differen

Page 41 - NKE0068A

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comOPERATING RATINGS(1)(2)Operating Temperature Range 0°C to +70°CSupply Voltage (VA=VD) +1.

Page 42

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013ELECTRICAL CHARACTERISTICS (continued)Unless otherwise specified, the following condition

Page 43

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comELECTRICAL CHARACTERISTICS (continued)Unless otherwise specified, the following condition

Page 44 - IMPORTANT NOTICE

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013EXTERNAL INPUT CLOCK AND PLL CHARACTERISTICS (continued)Unless otherwise specified, the f

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