Delta 45 Specifications Page 1

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013ADC12EU050 Ultra-Low Power, Octal, 12-bit, 45 MSPS Sigma-Delta Analog-to-DigitalConverter

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comAC AND TIMING CHARACTERISTICSUnless otherwise specified, the following conditions apply:

D1 D2 D3 D4 D5D6D7 D9D8 D11 D0 D1 D2 D3D11D10 D4 D5BCLK+WCLK-Output dataSystem ClocktHtStBCLKtDVtRSample nSample n+1WCLK+BCLK-DOn+DOn-Word ClockBit Cl

tRStRHA7 D7 D0tSSELHI,,SCLKSDATASSELA7D7 D0SCLKSDATASSEL90%10%90%10%tSCLKRtSCLKFtSSELStSCLKtSCLKLtWStWHtSSELHtSCLKHR/WVDRVOCM0Differential output sign

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013FUNCTIONAL DESCRIPTIONThe ADC12EU050 employs a number of unique strategies to provide a h

OPAMPVIN+VIN-CLKOPAMPVIN+VIN-CLKCLKCLKCLKCLKADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comFigure 6. SHA Input StageFigure 7. Continuous

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Figure 8. Instant Overload RecoveryINTEGRATED PRECISION LC PLLThe ADC12EU050 family inclu

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comSuch steep digital filters introduce group delay problems, but the ADC12EU050 includes a

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013UNCORRELATED NOISE REFERENCE FOR EACH CHANNELIn many early multi-channel ADC designs, a s

-80-60-40-200GAIN (dB)101102103104105OFFSET (Hz)2040106107108Loop Bandwidth at 0.415 MHzLoop Bandwidth at 1.50 MHz-80-60-40-200GAIN (dB)10110210310410

1st stage of ÐÂ ModulatorVIN+VIN-ADC1st stage of ÐÂ ModulatorVIN+VIN-ADCVCMRecommended transformer:Mini-circuits T1-6TADC12EU050www.ti.comSNAS444I –JA

SLEEPRSTReference and BiasRefselectIRef0.5VCLK+ (SE)CLK-VINn+VREFTVREFBRREFSDATASCLKDCRegisterADC12EU050DOn+DOn-RegisterTo RegistersCMOS INSPI Control

1st stage of ÐÂ ModulatorVIN+VIN-ADCDifferential Input pDifferential Input nREXTREXTADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comThe A

LVDSClassic full bridgeBias PBias NVDR = 1.8VVIN+VIN-VOCM = 1.25VVOUT+Optional internal 1005 terminationVOUT-Reduced Common Mode LVDSHalf BridgeVDD Re

SLVSHalf BridgeVSS ReferencedBias PVDR = 1.2VVIN+VIN-VOCM = 175 mVVOUT+Optional internal 1005 terminationVOUT-ADC12EU050SNAS444I –JANUARY 2008–REVISED

CH0 SerializerCH7 SerializerTSEL[0]TSEL[1]From Decimator Control Register 16hTraining Sequence 3:Custom PatternTraining Sequence 2:101010101010Trainin

ADC1RREFVREFTVREFBADC2RREFVREFTVREFBADCnRREFVREFTVREFBAGNDplane10 k5(± 1%)10 k5(± 1%)10 k5(± 1%)Digital Filter saturates at IOR mode full scale, deter

DCAPDACBiasDACRDCAPCDCAP1.5 k5ADC12EU050 ä? ModulatorAGNDADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013DCAPCAPACITOR SELECTIONThe DCAPp

100 nF505100 nF100 nF100 nF47 µFVIN0+VIN0-VIN1+VIN1-CLK+ (SE)CLK-VREFTVREFBDCAPRSTSLEEPSSELSCLKSDATADO0+DO0-DO1+DO1-DO2+DO2-DO3+DO3-DO4+DO4-DO5+DO5-DO

ADCSPIController(Master)e.g. DSP,Microcontroller,FPGAserial_inclockchip_select_b_1serial_outoutput_enableVDADCSDATASCLKSSELchip_select_b_NSDIO Pads co

If R/W = 1 (read), the SPI drives SDATA.If R/W = 0 (write), SDATA is driven from externally.SDATA is driven from externallySDATASSELSCLKA7 A6 A5 A4 A3

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Register IndexAddress b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] DefaultTop Control Register

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 521234567891011121314151617515049484746454443424140393837363518 19 20 21 22 23 24 25 26 27 28 29 30 31

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comBit DescriptionThe SRES is self clearing in approximately 2µs.0 Software Reset Inactive1

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Bit Description1 PD1: Power Down Channel 10 Channel Active1 Channel Power Down0 PD0: Powe

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comPLL Control Register• Address: 08h• Attributes: Write Only• Register 09h reads back conte

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Bit Description2 20HYS: Enable 20mV hysteresis. This bit enables 20mV hysteresis. It shou

DGF = 32 + 4 x DGFa + DGFb26ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comDecimator Clipping Control Register• Address: 14h• Attributes

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Coefficent a[2:0] Coefficent b[2:0] Digital Gain (dB) Equivalent full scaleinput range (V

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comBit Description1:0 TSEL[1:0]: Training Sequence Select. These bits select the LVDS output

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013Chip ID Register• Address: 1Eh• Attributes: Read Onlyb[7] b[6] b[5] b[4] b[3] b[2] b[1] b

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comREVISION HISTORYChanges from Revision H (April 2013) to Revision I Page• Changed layout o

PACKAGE OPTION ADDENDUMwww.ti.com13-Sep-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEc

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comPIN DESCRIPTIONSPin No. Name Type Function and ConnectionANALOG I/O2 VIN0+3 VIN0-67 VIN1+

PACKAGE OPTION ADDENDUMwww.ti.com13-Sep-2014Addendum-Page 2

www.ti.comPACKAGE OUTLINECPIN 1 ID0.9 MAX0.050.004X868X 0.30.264X 0.568X 0.70.54X (45 X0.42)7.7 0.1B10.19.9A10.19.9(0.2)VQFN - 0.9 mm max heightNKE00

www.ti.comEXAMPLE BOARD LAYOUT68X (0.8)68X (0.25)( 7.7)(9.6)64X (0.5)( ) TYPVIA0.20.07 MAXALL AROUND0.07 MINALL AROUND(9.6)(1.19) TYP(1.19)TYPVQFN - 0

www.ti.comEXAMPLE STENCIL DESIGN(9.6)68X (0.8)68X (0.25)64X (0.5)(1.19) TYP(1.19)TYP(9.6)36X(0.99)VQFN - 0.9 mm max heightNKE0068APLASTIC QUAD FLATPAC

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013PIN DESCRIPTIONS (continued)Pin No. Name Type Function and ConnectionWord Clock. Differen

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comOPERATING RATINGS(1)(2)Operating Temperature Range 0°C to +70°CSupply Voltage (VA=VD) +1.

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013ELECTRICAL CHARACTERISTICS (continued)Unless otherwise specified, the following condition

ADC12EU050SNAS444I –JANUARY 2008–REVISED APRIL 2013www.ti.comELECTRICAL CHARACTERISTICS (continued)Unless otherwise specified, the following condition

ADC12EU050www.ti.comSNAS444I –JANUARY 2008–REVISED APRIL 2013EXTERNAL INPUT CLOCK AND PLL CHARACTERISTICS (continued)Unless otherwise specified, the f