Delta 45 Specifications download pdf (Page 15)

ADC12EU050

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SNAS444I –JANUARY 2008–REVISED APRIL 2013

Figure 8. Instant Overload Recovery

INTEGRATED PRECISION LC PLL

The ADC12EU050 family includes an integrated high performance “clean up” phase locked loop (PLL),

simplifying the need for a low jitter external clock. The PLL serves three important functions; it generates a highly

accurate internal sampling clock source of up to 720 MHz; a clock for the LVDS serializers at 540 MHz; and it

provides a low jitter clock for other internal components. With its jitter clean-up capability this PLL allows lower

performance system clocks to be used.

DIGITAL DECIMATION FILTER AND EQUALIZER

The digital decimation filter is an integral part of the sigma delta architecture. It decimates the over-sampled data

from the modulator down to the sample rate, and its extremely sharp low pass characteristic combined with the

modulator’s broad band response provides the intrinsic anti-alias filter. The digital low pass filter exhibits 72dB of

attenuation in the stop band. The following diagram shows the digital filter transfer function at 40MSPS,

compared to a third order Butterworth transfer function. Due to the digital implementation of the filter, the filter

parameters automatically scale with the ADC sampling frequency.

Figure 9. Digital Filter Transfer Function

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Delta 45 Specifications Page 15