ADC12EU050
www.ti.com
SNAS444I –JANUARY 2008–REVISED APRIL 2013
UNCORRELATED NOISE REFERENCE FOR EACH CHANNEL
In many early multi-channel ADC designs, a single voltage reference was used to provide the reference level for
each channel. Unfortunately, this ensures that the noise at each ADC’s reference terminal is cross correlated.
Multi-channel systems often make use of a 3 dB processing gain increase that results from each channel
doubling. Without a specific technique to prevent the reference terminals seeing correlated noise the expected 3
dB gain is compromised. In the case of the ADC12EU050, a unique system has been implemented to de-
correlate the noise at each ADC channel.
APPLICATION INFORMATION
POWER-UP SEQUENCE
The ADC12EU050 has three separate power supplies: Analog (V
A
), Digital (V
D
) and the output drive voltage (
V
DR
). The ADC contains a power on reset circuit, connected to VA, and so to ensure correct reset of both analog
and digital logic of the ADC, the power supplies should be provided in the following order:
1. V
DR
2. V
D
3. V
A
If this order is not followed, then the user should issue a reset via the reset pin (RST) immediately after power
up. Additionally, it is required that the rise time for each voltage supply is longer than the minimum rise time
stated in the ELECTRICAL CHARACTERISTICS.
There is no required sequence for powering down the ADC.
ADC START-UP SEQUENCE
After any reset, either power-on reset, software reset via SPI or hardware reset via the RST pin, the chip
undergoes a series of internal calibrations and the PLL/VCO will lock to the external clock.
After reset, the ADC12EU050’s registers have the default values shown in register tables. The registers can be
programmed via the SPI after reset, even during the period while the chip is performing the internal calibrations
mentioned in the previous paragraph.
During reset and until the PLL is locked, the LVDS outputs will not provide valid data. Furthermore, the ADC has
an inherent data conversion latency, which is related to the pipeline stages of the digital decimating filter. Until
the data conversion latency has passed, the data outputs will be invalid.
Thus the maximum time until valid sampled data is received at the outputs is:
PLL lock time + ADC Latency
Specific values for these times can be found in the ELECTRICAL CHARACTERISTICS.
USING ADC LOW POWER MODES
As explained previously in FUNCTIONAL DESCRIPTION, the ADC12EU050 offers several power management
modes.
Sleep mode offers the fastest wake-up time, and should be used in applications where duty cycle powering of the
ADC is required. In this case it is recommended to toggle sleep mode via the SLEEP pin, which will give a faster
cycle time than programming the SLEEP bit through the SPI, due to the extra time required to send a command
through the SPI port.
The Power Down mode is accessible via the SPI port. Due to the power-up time of the ADC coupled with the
programming time of the SPI port, this mode should be used to power the chip down for longer time periods.
Channel power down allows one or more channels to be turned off independently, with the corresponding power
saving.
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