Delta 45 Specifications download pdf (Page 2)

SLEEP

RST

Reference and Bias

Ref

select

I

Ref

0.5V

CLK+ (SE)

CLK-

V

IN

n+

V

REFT

V

REFB

R

REF

S

DATA

S

CLK

DC

Register

ADC12EU050

DOn+

DOn-

Register

To Registers

CMOS IN

SPI Control

ADC

CONTROL

Register

Digital Decimation Filter

Output

LVDS

SLVS

CTÐ?

Modulator

Clipping Control

3 bit

1 bit

V

A

AGND

V

D

DGND

1.2V

1.2V

S

SEL

LVDS

Input

PLL

Register

LC

VCO

1.3 kÖ

12 bit

Serializer

Register

Register Register Register

Output

LVDS

SLVS

WCLK-

WCLK+

BCLK-

BCLK+

1.2V to 1.8V

V

DR

DGND

Output

LVDS

SLVS

1.3 kÖ

V

IN

n-

D

CAP

8 times

ADC12EU050

SNAS444I –JANUARY 2008–REVISED APRIL 2013

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Block Diagram

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