If R/W = 1 (read), the SPI drives S
DATA
.
If R/W = 0 (write), S
DATA
is driven from externally.
S
DATA
is driven from externally
S
DATA
S
SEL
S
CLK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0R/W
ADC12EU050
SNAS444I –JANUARY 2008–REVISED APRIL 2013
www.ti.com
Figure 27. Serial Control Interface Protocol
The eight address bits, A[7:1] + R/W, are sent first. The data, D[7:0], is then sent for a write transaction, or D[7:0]
is received for a read transaction. Address and data are sent and received with the most-significant-bit (MSB)
first. The SPI is enabled using the active low input S
SEL
. If S
SEL
is high the SPI cannot be accessed, although
S
SEL
is not a reset signal and registers will maintain their value when S
SEL
is toggled. S
SEL
must be held low
during the entire transaction.
Timing requirements for the Serial Interface are described in ELECTRICAL CHARACTERISTICS.
SERIAL INTERFACE TRANSACTION CANCELLATION
A transaction may be cancelled before the address and data stages are completed by toggling S
SEL
to high at
any stage during an SPI access. This action is not recommended, as transaction cancellation during a write
transaction may corrupt register contents and during a read transaction will result in incorrect data.
After canceling a transaction with S
SEL
the ADC may be in an unknown state due to an incomplete and hence
corrupted write to a register. It is therefore recommended to reset the chip via Software Reset (SRES) after a
cancelled transaction.
S
DATA
PAD OPEN DRAIN MODE
If the S
DATA
voltage at the board level is required to be higher than the ADC12EU050’s V
DR
, the Open Drain
mode should be used. In Open Drain mode, the ADC’s S
DATA
will pull the output low, and S
DATA
will be pulled up
to the external level by a pull-up resistor connected to the board’s positive voltage rail, VEXT.
The intended use of Open Drain mode is when the ADC, including V
DR
, is running at 1.2V, and a VEXT of 1.8V
is required.
Open Drain mode is enabled by setting the SPIOD bit in the Top Control Register via the Serial Interface. When
in Open Drain mode, a pull-up resistor (RSDATA) must be connected between S
DATA
and VEXT. ELECTRICAL
CHARACTERISTICS shows the required settings for VEXT and RSDATA.
SERIAL CONTROL INTERFACE READ AND WRITE SPEED
S
CLK
(pin 45) controls the speed of interaction with the ADC. The SPI interface supports write to and read from
speeds as defined in the ELECTRICAL CHARACTERISTICS.
SERIAL CONTROL INTERFACE REGISTER DESCRIPTIONS
The following tables show the complete set of user accessible SPI registers, with descriptions of the functionality
of each bit.
Reset values of all registers are also described in the tables below.
28 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
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