Delta 45 Specifications Page 33

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ADC12EU050
www.ti.com
SNAS444I JANUARY 2008REVISED APRIL 2013
Bit Description
2 20HYS: Enable 20mV hysteresis. This bit enables 20mV hysteresis. It should be used for an LVDS input
clock only.
0 Normal operation (10mV hysteresis)
1 20mV hysteresis. (LVDS input clock only)
1 10HYSOFF: Disable 10mV hysteresis. 10mV hysteresis is the default setting. This bit is used to disable
10mV hysteresis, in the case where another hysteresis setting is desired, for example when using a CMOS
input clock.
0 10mV hysteresis. (LVDS input clock only)
1 10mV hysteresis disabled.
0 HYSOFF: Disable all hysteresis settings. This bit is used to disable all hysteresis settings.
0 Normal operation (10mV hysteresis)
1 All hysteresis settings disabled.
Serializer Custom Pattern 0 Register
Address: 10h
Attributes: Write Only
Register 11h reads back contents of Register 10h
This register in conjunction with User Register 12 provides storage for the custom de-skew pattern. See User
Register 16 for a description of how this training sequence is used.
b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] HEX
Description Custom Pattern [7:0]
Default 0 0 0 0 0 0 0 0 00 h
Bit Description
7:0 Custom Pattern [7:0]. This pattern forms the lower byte of Custom Pattern [11:0] which is output by the
serializer when the Training Sequence Select bits (bits 1:0) of the Decimator Control Register are set to select
Training sequence 3.
Serializer Custom Pattern 1 Register
Address: 12h
Attributes: Write Only
Register 13h reads back contents of Register 12h
This register in conjunction with User Register 10 provides storage for the custom de-skew pattern. See User
Register 16 for a description of how this training sequence is used.
b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] HEX
Description Reserved Custom Pattern [11:8]
Default 0 0 0 0 0 0 0 0 00 h
Bit Description
7:4 Reserved. Write as zero for future compatibility.
3:0 Custom Pattern [11:8]. This pattern forms the upper 4 bits of Custom Pattern [11:0] which is output by the
serializer when the Training Sequence Select bits (bits 1:0) of the Decimator Control Register are set to select
Training sequence 3.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 33
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