ADC12EU050
SNAS444I –JANUARY 2008–REVISED APRIL 2013
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Bit Description
1:0 TSEL[1:0]: Training Sequence Select. These bits select the LVDS output data.
The default mode of operation is where the filter output data is serialized.
In the remaining modes the selected training sequence is repeatedly output from the serializer this allows the
receiving data capture circuitry to perform the de-skewing process.
One of three known words can be selected, the first two words are hard-coded in the block, the third one, the
custom pattern, is written into User Registers 10h and 12h the Serializer Custom Pattern Registers.
Note: The outputs bit-clock and word-clock are not affected by the value of the Training Sequence Select bits.
00 ADC data[11:0]
01 Training sequence 1: 000000111111
10 Training sequence 2: 101010101010
11 Training sequence 3: custom pattern
LVDS Control Register
• Address: 18h
• Attributes: Write Only
• Register 19h reads back contents of register 18h
b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] HEX
Description Reserved TX_term I_drive[1:0] OCM SLVS
Default 0 0 0 0 0 0 0 0 00 h
Bit Description
7:5 Reserved. Write as zero for future compatibility.
4 TX_term: Enable Internal 100 Ohm termination for data outputs.
0 Internal 100 ohm termination disabled
1 Internal 100 ohm termination enabled
3:2 I_drive[1:0]: Controls the current drive of the data outputs.
00 2.5 mA
01 3.5 mA
10 Reserved
11 5 mA
1 OCM: Output Common mode. Allows the output common mode to be shifted depending on the setting of V
DR
.
If bit 0 of this register, SLVS, is set to 1 then changing OCM will have no impact on the output common mode.
The output common mode in SLVS mode is fixed, as described in the ELECTRICAL CHARACTERISTICS.
For V
DR
= 1.2V, OCM must be set to 0.
For V
DR
= 1.8V, OCM must be set to 1.
0 Output Common Mode, V
OCM
= 1.0V
1 Output Common Mode, V
OCM
= 1.25V
0 SLVS: Select the format for output data, either LVDS or SLVS. The differences in timing and electrical
specifications between the two modes can be seen in the ELECTRICAL CHARACTERISTICS.
If this bit is set to 1 (SLVS mode), OCM has no effect and the output common mode will be set for SLVS as
described in the ELECTRICAL CHARACTERISTICS.
When LVDS mode is selected, the output common mode must be selected using the OCM bit of this register.
0 LVDS Mode
1 SLVS Mode
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