ADC12EU050
SNAS444I –JANUARY 2008–REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS
Pin No. Name Type Function and Connection
ANALOG I/O
2 V
IN
0+
3 V
IN
0-
67 V
IN
1+
68 V
IN
1-
64 V
IN
2+
65 V
IN
2-
61 V
IN
3+ Differential analog inputs to the ADC, for channels 0 to 7. The
62 V
IN
3- negative input pin may be connected via a capacitor to AGND or the
Input
58 V
IN
4+ inputs may be transformer coupled for single ended operation.
59 V
IN
4- Differential inputs are recommended for best performance.
55 V
IN
5+
56 V
IN
5-
52 V
IN
6+
53 V
IN
6-
49 V
IN
7+
50 V
IN
7-
Optional negative reference voltage to improve multi-channel ADC
4 V
REFB
matching. This pin must be connected to AGND.
Optional positive reference voltage to improve multi-channel ADC
matching. If using the internal reference, this pin should be left tied
to AGND through a 100nF capacitor. If using an external reference
5 V
REFT
voltage, this pin should be connected to the positive reference
voltage, which must lie in the range specified in the Electrical
Characteristics table.
This pin provides the capacitance for the low pass filter in the
modulator’s DAC. It must be connected to AGND through a minimum
100nF capacitor. It is possible to decrease the noise close to the
6 D
CAP
Input
carrier by increasing this capacitor, up to a maximum of 10μF. See
APPLICATION INFORMATION for further information on the
selection of this capacitor.
External bias reference resistor. This pin must always be connected
to AGND through a resistor, whether the internal reference or an
7 R
REF
Input/Output
external reference voltage is used. The resistor value must be 10kΩ
±1%.
DIGITAL I/O
This pin is an active low reset for the entire ADC, both analog and
9 RST Input digital components. The pin must be held low for 500ns then
returned to high in order to ensure that the chip is reset correctly.
Sleep mode. Toggling this pin to high will cause the ADC to enter the
low power sleep mode. When the pin is returned to low, the chip will,
10 SLEEP Input
after the specified time to exit sleep mode, return to normal
operation.
15 DO0+
16 DO0-
18 DO1+
19 DO1-
20 DO2+
Differential Serial Outputs for channels 0 to 7. Each pair of outputs
21 DO2-
provides the serial output for the specific channel. The default output
23 DO3+
is reduced common mode LVDS format, but by programming the
24 DO3-
Output appropriate control registers, the output format can be changed to
25 DO4+
SLVS or LVDS.
26 DO4-
By programming TX_term (bit 4) in the LVDS Control register, it is
28 DO5+
possible to internally terminate these outputs with 100 ohm resistors.
29 DO5-
31 DO6+
32 DO6-
33 DO7+
34 DO7-
Bit clock. Differential output clock used for sampling the serial
outputs. Information on timing can be seen in the ELECTRICAL
36 BCLK+
Output CHARACTERISTICS.
37 BCLK-
By programming TX_term (bit 4) in the LVDS Control register, it is
possible to internally terminate these outputs with 100 ohm resistors.
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