ADC12EU050
SNAS444I –JANUARY 2008–REVISED APRIL 2013
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, the following conditions apply: V
A
= V
D
= 1.2V; V
DR
= 1.2V; V
REF
= internal; R
REF
= 10kohm ±1%;
C
L
= 5pF; 100Ω terminated at the receiver; f
CLK
= 45MHz; f
S
= 45MSPS. Boldface limits apply for T
A
= T
MIN
to T
MAX
; All other
limits apply for T
A
= +25°C.
Symbol Parameter Conditions Typical
(1)
Limits Units
Recovery time from sleep 12 µs (max)
Recovery time from power down 18 ms (max)
Recovery time from single channel 6 µs (max)
power down
DIGITAL DECIMATION FILTER CHARACTERISTICS
Unless otherwise specified, the following conditions apply: V
A
= V
D
= 1.2V; V
DR
= 1.2V; V
REF
= internal; R
REF
= 10kohm ±1%;
C
L
= 5pF; 100Ω terminated at the receiver; f
CLK
= 45MHz; f
S
= 45MSPS. Boldface limits apply for T
A
= T
MIN
to T
MAX
; All other
limits apply for T
A
= +25°C.
Typical
(2
Symbol Parameter Conditions
(1)
Limits Units
)
Pass Band f
CLK
= 45MHz 19.8 MHz
Pass Band Transition f
CLK
= 45MHz, -3dB attenuation 22.5 MHz
Pass Band Ripple f
IN
< 22MHz ±0.01 dB
Stop Band Begin f
CLK
= 45MHz 31.05 MHz
Stop Band Attenuation 72 dB (min)
Group Delay Ripple (peak to peak) f
IN
< 22MHz, Equalizer on 0.05 Samples (max)
(1) As the filter is a digital circuit, Digital Decimation Filter Characteristics scale with input clock frequency, f
CLK
.
(2) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
EXTERNAL INPUT CLOCK AND PLL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: V
A
= V
D
= 1.2V; V
DR
= 1.2V; V
REF
= internal; R
REF
= 10kohm ±1%;
C
L
= 5pF; 100Ω terminated at the receiver; f
CLK
= 45MHz; f
S
= 45MSPS. Boldface limits apply for T
A
= T
MIN
to T
MAX
; All other
limits apply for T
A
= +25°C.
Symbol Parameter Conditions Typical
(1)
Limits Units
External Input Clock
45 MHz (min)
f
CLK
Allowed input clock frequency
45.5 MHz (max)
t
CLK
Allowed input clock period 1/f
CLK
ns
20 % (min)
f
CLK
DC Allowed input clock duty cycle 50
80 % (max)
Allowed RMS clock jitter on input
t
JIN
Integrated from 10Hz to BW
loop
300 fs rms
clock.
400 mV (min)
V
CMCLK
Allowed input clock common mode See
(2)
VDR mV (max)
mV peak-peak
200
(min)
V
ICLK
Allowed input clock voltage swing Differential clock input.
(2)
400
mV peak-peak
VDR
(max)
PLL
712 MHz (min)
f∑Δ Over-sampling frequency
728 MHz (max)
(1) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(2) The combination of common mode and voltage swing on the clock input must ensure that the positive voltage peaks are not above VDR
and the negative votlage peaks are not below AGND.
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