ADC12EU050
SNAS444I –JANUARY 2008–REVISED APRIL 2013
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PLL Control Register
• Address: 08h
• Attributes: Write Only
• Register 09h reads back contents of register 08h
b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] HEX
Description Reserved SHBW STCAL
Default 0 0 0 0 0 0 0 0 00 h
Bit Description
7:2 Reserved. Write as zero for future compatibility.
1 SHBW: Set PLL to High Bandwidth. The selection of the PLL bandwidth permits to set the sensitivity of the
PLL to input clock jitter. Less bandwidth decreases the sensitivity to input clock jitter.
The PLL Bandwidth is related to the sampling frequency, the exact values of which can be found in
ELECTRICAL CHARACTERISTICS.
The PLL will pass any input clock jitter up to the PLL bandwidth, while jitter above the PLL bandwidth will be
attenuated. Low bandwidth mode should be used for high jitter input clocks, while high bandwidth mode can be
used for high-quality, low jitter input clocks.
0 PLL bandwidth is set to Low Bandwidth (400kHz).
1 PLL bandwidth is set to High Bandwidth (1.4MHz).
0 STCAL: Start VCO calibration. The calibration can be manually started in order to assure that the frequency
tuning margin is maximum, for example, in case of large temperature change during operation it can be useful
to restart the calibration.
0 The VCO calibration starts automatically if a Loss of Lock is detected
1 The VCO calibration is restarted.
LVDS Input Clock – Hysteresis
• Address: 0Ah
• Attributes: Write Only
• Register 0Bh reads back contents of register 0Ah
b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] HEX
10HYS
Description Reserved INVCLK 100HYS 50HYS 20HYS HYSOFF
OFF
Default 0 0 0 0 0 0 0 0 00 h
Bit Description
7:6 Reserved. Write as zero for future compatibility.
5 INVCLK: Invert Input Reference Clock. This bit is used to invert the input clock.
0 Reference input clock not inverted.
1 Reference input clock inverted.
4 100HYS: Enable 100mV hysteresis. This bit enables 100mV hysteresis. It should be used for a CMOS input
clock only.
0 Normal operation (10mV hysteresis)
1 100mV hysteresis (CMOS input clock only)
3 50HYS: Enable 50mV hysteresis. This bit enables 50mV hysteresis. It should be used for a CMOS input clock
only.
0 Normal operation (10mV hysteresis)
1 50mV hysteresis. (CMOS input clock only)
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